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EP/I004157/2 - Breaking the Copper Bottleneck: Computer Architecture and Power Implications of Photonic Interconnect

Research Perspectives grant details from EPSRC portfolio

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Dr P WATTS EP/I004157/2 - Breaking the Copper Bottleneck: Computer Architecture and Power Implications of Photonic Interconnect

Principal Investigator - Electronic and Electrical Engineering, University College London

Scheme

Career Acceleration Fellowship

Research Areas

Microelectronics Design Microelectronics Design

Optical Communications Optical Communications

Collaborators

Xilinx Corp Xilinx Corp

Start Date

06/2011

End Date

09/2015

Value

£588,413

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Grant Description

Summary and Description of the grant

The provision of future services in the digital economy is reliant on achieving more power efficient computers. Recent bandwidth improvements in electronic interconnects have only been achieved at the expense of dramatic increases in latency and power consumption [19]. Photonic technologies appear essential to make chip-to-chip communication sustainable for ever-higher data rates due to inherently lower power operation. Recent advances in silicon photonics, photonic printed circuit boards (PCB) and 3D integration technologies indicate great promise for short distance photonics. However, given the radical changes in computer design brought about by chip multiprocessors (CMP) and the fundamental differences between electronic and photonic communications, the design implications for complete computer systems are not clear. The proposed research will study the implications of upcoming photonic technologies on the power consumption and architecture of large computer systems such as high performance computers and data centres. The uniqueness of the proposal is its method and the holistic results that it should produce. I will start with a firm scientific foundation based on characterisation of emerging photonic devices leading to models of existing and predicted future components. FPGA-based emulation will enable investigation of complete multi-chip, multi-core computer systems and interconnect running at around 1/100th of real time. The outcome will be the knowledge to build large computer systems optimised for minimum power consumption. This multidisciplinary research therefore underpins several EPSRC themes: digital economy, next-generation healthcare and energy efficiency as well as responding to the EPSRC signposted Moore-for-Less microelectronic grand challenge.

Structured Data / Microdata


Grant Event Details:
Name: Breaking the Copper Bottleneck: Computer Architecture and Power Implications of Photonic Interconnect - EP/I004157/2
Start Date: 2011-06-01T00:00:00+00:00
End Date: 2015-09-30T00:00:00+00:00

Organization: University College London

Description: The provision of future services in the digital economy is reliant on achieving more power efficient computers. Recent bandwidth improvements in electronic interconnects have only been achieved at the expense of dramatic increases in latency and power con ...